entity pipeline_instruction is
  port(
    DATA_IN     : in std_logic_vector(11 downto 0);
    CLK_i       : in std_logic;
    DATA_OUT    : out std_logic_vector(11 downto 0)
  );
end pipeline_instruction;

architecture structural of pipeline_instruction is

  component reg_inst
    port(
      D_i     : in std_logic_vector(11 downto 0);
      CLK_i   : in std_logic;
      Q_o     : out std_logic_vector(11 downto 0) );
  end component;

  signal data: std_logic_vector(11 downto 0);

begin
	U1 : reg_inst port map( 
		D_i   => DATA_IN,
		CLK_i => CLK_i,
		Q_o   => data );

	U2 : reg_inst port map(
		D_i   => data,
		CLK_i => CLK_i,
		Q_o   => DATA_OUT );

	DATA_OUT <= data;
end structural;
